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| july 2007 hys72t1g242ep?[25f/2.5]?c hys72t1g242ep?[3/3s/3.7]?c 240-pin dual die registered ddr2 sdram modules rdimm sdram rohs compliant internet data sheet rev. 1.0
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5]?c, hys72t1g242ep?[3/3s/3.7]?c revision history: 2007-07, rev. 1.0 page subjects (major chan ges since last revision) all adapted to internet version all final document internet data sheet rev. 1.0, 2007-07 3 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 1overview this chapter gives an overview of the 1.8 v 240-pin dua l die registered ddr2 sdram modules with parity bit product family and describes its main characteristics. 1.1 features ? 240-pin pc2?6400, pc2?5300 and pc2?4200 ddr2 sdram memory modules. ? 1024m 72 module organization and 512m 4 chip organization ? registered dimm parity bit for address and control bus ? 8 gbyte modules built with stacked 2 gbit (1gbit dual dies) ddr2 sdrams in p-tf bga-63 chipsize packages. ? standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply ? programmable cas latencies (3 , 4, 5, 6), burst length (4 & 8) ? auto refresh (cbr) and self refresh ? programmable self refres h rate via emrs2 setting ? programmable partial array refresh via emrs2 settings ? dcc enabling via emrs2 setting ? all inputs and outputs sstl_18 compatible ? off-chip driver impedance adjustment (ocd) and on-die termination (odt) ? serial presence detect with e 2 prom ? rdimm dimensions (nominal): 30 mm high, 133.35 mm wide ? based on standard reference card layouts raw card ?z? ? all speed grades faster than ddr2?400 comply with ddr2?400 timing specifications. ? rohs compliant products 1) table 1 performance table 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed code ?25f ?2.5 ?3 ?3s ?3.7 unit dram speed grade ddr2?800d ddr2?800e ddr2?667c ddr2?667d ddr2?533c speed grade pc2?6400 pc2?6400 pc2?5300 pc2?5300 pc2?4200 cas-rcd-rp latencies 5-5-5 6-6-6 4-4-4 5-5-5 4-4-4 t ck max. clock frequency @cl6 f ck6 ?400???mhz @cl5 f ck5 400 333 333 333 266 mhz @cl4 f ck4 266 266 333 266 266 mhz @cl3 f ck3 200 200 200 200 200 mhz min. ras-cas-delay t rcd 12.515121515ns min. row precharge time t rp 12.515121515ns min. row active time t ras 45 45 45 45 45 ns min. row cycle time t rc 57.560576060ns internet data sheet rev. 1.0, 2007-07 4 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 1.2 description the qimonda hys72t1g242ep?[25f/2.5/3//3s/3.7]?c module family are registered dimm (with parity) modules with 30 mm height based on ddr2 technology. dimms are available as ecc modules in 1024m 72 (8 gb) organization and density, intend ed for mounting into 240-pin connector sockets. the memory array is designed with stacked 2 gbit (1gbit dual dies) double-data-rate-two (ddr2) synchronous drams. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. decoupling capacitors are mounted on the pcb board. the dimms feature serial presence detect based on a serial e2prom device using the 2-pin i2c prot ocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. table 2 ordering information for rohs compliant products table 3 address format table 4 components on modules product type 1) 1) all product type number end with a place code, designating the silicon die revision. example: h ys72t1g242ep-3.7-c, indicating rev. ?c? dies are used for ddr2 sdram components. for all qimonda ddr2 module and component nomenclature see chapter 6 of this data sheet. compliance code 2) 2) the compliance code is printed on the module label and describes the speed grade, for example ?pc2?4200p?444?12?zz?, where 42 00p means registered dimm modules (with parity bit) with 4.26 gb /sec module bandwidth and ?444-12? means column address strobe (cas) latency = 4, row column delay (rcd) latency = 4 and row precharge (rp) latency = 4 using the latest jedec spd revision 1.2 and produced on the raw card ?f? description sdram technology pc2?6400 hys72t1g242ep-2.5-c 8gb 4rx4 pc2-6400p-666-12-zz 4 rank, ecc 1gbit ( 4) hys72t1g242ep-25f-c 8gb 4rx4 pc2-6400p-555-12-zz 4 rank, ecc 1gbit ( 4) pc2?5300 hys72t1g242ep-3-c 8gb 4rx4 pc2-5300p-444-12-zz 4 rank, ecc 1gbit ( 4) hys72t1g242ep-3s-c 8gb 4rx4 pc2-5300p-555-12-zz 4 rank, ecc 1gbit ( 4) pc2?4200 hys72t1g242ep-3.7-c 8gb 4rx4 pc2-4200p-444-12-zz 4 rank, ecc 1gbit ( 4) dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/column bits raw card 8 gbyte 1024m 72 4 ecc 36ddp 1) 1) ddp dual die package 14/3/11 z product type 1) 1) for a detailed description of all functionalities of the dram components on these modules see the component data sheet. dram components dram density dram organization hys72t1g242ep hyb18t2g402cf 1 gbit 2 512m 4 internet data sheet rev. 1.0, 2007-07 5 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 2 pin configuration and block diagrams this chapter contains the pin configuration and block diagrams. 2.1 pin configuration the pin configuration of the registered ddr2 sdram dimm is listed by function in table 5 (240 pins). the abbreviations used in columns pin and buffer type are explained in table 6 and table 7 respectively. the pin numbering is depicted in figure 1 . table 5 pin configuration of rdimm pin no. name pin type buffer type function clock signals 185 ck0 i sstl clock signal ck0, comple mentary clock signal ck0 the system clock inputs. all address and command lines are sampled on the cross point of the rising edg e of ck and the falling edge of ck . a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. 186 ck0 isstl 52 cke0 i sstl clock enables 1:0 activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deacti vating the clocks, cke0 initiates the power down mode or the self refresh mode. note: 2-ranks module 171 cke1 i sstl nc nc ? not connected note: 1-rank module control signals 193 s0 isstl chip select enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s0 rank 1 is selected by s1 the input signals also disable all outputs (except cke and odt) of the register(s) on the dimm when both inputs are high. when s is high, all register outputs (except ck, odt and chip select) remain in the previous state. note: 2-ranks module 76 s1 isstl nc nc ? not connected note: 1-rank module internet data sheet rev. 1.0, 2007-07 6 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 220 s2 isstl rank 2 is selected by s2 nc nc ? not connected note: 1-rank, 2-ranks module 221 s3 isstl rank 3 is selected by s3 nc nc ? not connected note: 1-rank, 2-ranks module 192 ras isstl row address strobe (ras), column address strobe (cas), write enable (we) when sampled at the cross point of the rising edge of ck, and falling edge of ck , ras , cas and we define the operation to be executed by the sdram. 74 cas isstl 73 we isstl 18 reset icmos register reset the reset pin is connected to the rs t pin on the register and to the oe pin on the pll. when low, all register outputs will be driven low and the pll clocks to th e drams and the registe r(s) will be set to low- level. the pll will remain synchronized with the input clock. address signals 71 ba0 i sstl bank address bus 1:0 selects internal sdram memory bank 190 ba1 i sstl 54 ba2 i sstl bank address bus 2 greater than 512mb ddr2 sdrams nc i sstl not connected less than 1gb ddr2 sdrams 188 a0 i sstl address bus 12:0, address signal 10/autoprecharge during a bank activate command cycle, defines the row address when sampled at the crosspoint of the ri sing edge of ck and falling edge of ck . during a read or write comm and cycle, defines the column address when sampled at the cross po int of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at t he end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba[ 2:0] defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba[2:0] to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba[2:0] inputs. if ap is low, then ba[2:0] are used to define which bank to precharge. 183 a1 i sstl 63 a2 i sstl 182 a3 i sstl 61 a4 i sstl 60 a5 i sstl 180 a6 i sstl 58 a7 i sstl 179 a8 i sstl 177 a9 i sstl 70 a10 i sstl ap i sstl 57 a11 i sstl 176 a12 i sstl 196 a13 i sstl address signal 13 nc nc ? not connected note: non ca parity modules based on 256 mbit component pin no. name pin type buffer type function internet data sheet rev. 1.0, 2007-07 7 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 174 a14 i sstl address signal 14 note: ca parity module nc nc ? not connected note: non ca parity module. less than 1 gbit per dram die. 173 a15 i sstl address signal 14 note: ca parity module nc nc ? not connected note: non ca parity module. less than 1 gbit per dram die. data signals 3 dq0 i/o sstl data bus 63:0 data input/output pins 4 dq1 i/o sstl 9 dq2 i/o sstl 10 dq3 i/o sstl 122 dq4 i/o sstl 123 dq5 i/o sstl 128 dq6 i/o sstl 129 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 21 dq10 i/o sstl 22 dq11 i/o sstl 131 dq12 i/o sstl 132 dq13 i/o sstl 140 dq14 i/o sstl 141 dq15 i/o sstl 24 dq16 i/o sstl 25 dq17 i/o sstl 30 dq18 i/o sstl 31 dq19 i/o sstl 143 dq20 i/o sstl 144 dq21 i/o sstl 149 dq22 i/o sstl 150 dq23 i/o sstl 33 dq24 i/o sstl 34 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 152 dq28 i/o sstl 153 dq29 i/o sstl 158 dq30 i/o sstl pin no. name pin type buffer type function internet data sheet rev. 1.0, 2007-07 8 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 159 dq31 i/o sstl data bus 63:0 data input/output pins 80 dq32 i/o sstl 81 dq33 i/o sstl 86 dq34 i/o sstl 87 dq35 i/o sstl 199 dq36 i/o sstl 200 dq37 i/o sstl 205 dq38 i/o sstl 206 dq39 i/o sstl 89 dq40 i/o sstl 90 dq41 i/o sstl 95 dq42 i/o sstl 96 dq43 i/o sstl 208 dq44 i/o sstl 209 dq45 i/o sstl 214 dq46 i/o sstl 215 dq47 i/o sstl 98 dq48 i/o sstl 99 dq49 i/o sstl 107 dq50 i/o sstl 108 dq51 i/o sstl 217 dq52 i/o sstl 218 dq53 i/o sstl 226 dq54 i/o sstl 227 dq55 i/o sstl 110 dq56 i/o sstl 111 dq57 i/o sstl 116 dq58 i/o sstl 117 dq59 i/o sstl 229 dq60 i/o sstl 230 dq61 i/o sstl 235 dq62 i/o sstl 236 dq63 i/o sstl check bits 42 cb0 i/o sstl check bits 7:0 check bit input / output pins note: nc on non-ecc module 43 cb1 i/o sstl 48 cb2 i/o sstl 49 cb3 i/o sstl pin no. name pin type buffer type function internet data sheet rev. 1.0, 2007-07 9 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 161 cb4 i/o sstl check bits 7:0 check bit input / output pins note: nc on non-ecc module 162 cb5 i/o sstl 167 cb6 i/o sstl 168 cb7 i/o sstl data strobe bus 7 dqs0 i/o sstl data strobes 17:0 the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode the data strobe is sourced by the ddr2 sdram and is s ent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs. if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to v ss through a 20 ? to 10 k ? resistor and ddr2 sdram mode registers programmed appropriately. note: see block diagram for corresponding dq signals 6 dqs0 i/o sstl 16 dqs1 i/o sstl 15 dqs1 i/o sstl 28 dqs2 i/o sstl 27 dqs2 i/o sstl 37 dqs3 i/o sstl 36 dqs3 i/o sstl 84 dqs4 i/o sstl 83 dqs4 i/o sstl 93 dqs5 i/o sstl 92 dqs5 i/o sstl 105 dqs6 i/o sstl 104 dqs6 i/o sstl 114 dqs7 i/o sstl 113 dqs7 i/o sstl 46 dqs8 i/o sstl 45 dqs8 i/o sstl 125 dqs9 i/o sstl 126 dqs9 i/o sstl 134 dqs10 i/o sstl 135 dqs10 i/o sstl 146 dqs11 i/o sstl 147 dqs11 i/o sstl 155 dqs12 i/o sstl 156 dqs12 i/o sstl 202 dqs13 i/o sstl 203 dqs13 i/o sstl 211 dqs14 i/o sstl 212 dqs14 i/o sstl 223 dqs15 i/o sstl 224 dqs15 i/o sstl 232 dqs16 i/o sstl pin no. name pin type buffer type function internet data sheet rev. 1.0, 2007-07 10 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 233 dqs16 i/o sstl data strobes 17:0 164 dqs17 i/o sstl 165 dqs17 i/o sstl data mask 125 dm0 i sstl data masks 8:0 the data write masks, associated wit h one data byte. in write mode, dm operates as a byte mask by allowi ng input data to be wr itten if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. note: 8 based module 134 dm1 i sstl 146 dm2 i sstl 155 dm3 i sstl 202 dm4 i sstl 211 dm5 i sstl 223 dm6 i sstl 232 dm7 i sstl 164 dm8 i sstl eeprom 120 scl i cmos serial bus clock this signal is used to clock dat a into and out of the spd eeprom. 119 sda i/o od serial bus data this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resistor must be connected from sda to v ddspd on the motherboard to act as a pull-up. 239 sa0 i cmos serial address select bus 2:0 these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range 240 sa1 i cmos 101 sa2 i cmos parity 55 err_out ocmos parity bits note: only for modules with parity bit for address and control bus. not connected on non-parity registered modules. 68 par_in i cmos power supplies 1 v ref ai ? i/o reference voltage reference voltage for the sstl-18 inputs. 238 v ddspd pwr ? eeprom power supply serial eeprom positive po wer supply, wired to a separated power pin at the connector which supports from 1.7 volt to 3.6 volt. 51, 56, 62, 72, 75, 78, 170, 175, 181, 191, 194 v ddq pwr ? i/o driver power supply power and ground for the ddr sdram 53, 59, 64, 67, 69, 172, 178, 184, 187, 189, 197 v dd pwr ? power supply power and ground for the ddr sdram pin no. name pin type buffer type function internet data sheet rev. 1.0, 2007-07 11 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module table 6 abbreviations for buffer type 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 v ss gnd ? ground plane power and ground for the ddr sdram other pins 19, 102, 137, 138, nc nc ? not connected pins not connected on qimonda rdimm?s 195 odt0 i sstl on-die termination control 1:0 asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr2 sdram mode register. note: 2-ranks module 77 odt1 i sstl nc nc ? note: 1-rank modules abbreviation description sstl serial stub terminated logic (sstl_18) cmos cmos levels od open drain. the corresponding pin has 2 ope rational states, active low and tristate, and allows multiple devices to share as a wire-or. pin no. name pin type buffer type function internet data sheet rev. 1.0, 2007-07 12 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module table 7 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nu not usable nc not connected internet data sheet rev. 1.0, 2007-07 13 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module figure 1 pin configuration for rdimm (240 pins) 0 3 3 7 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 1 & 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 5 ( 6 ( 7 9 6 6 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 & % 9 6 6 ' 4 6 & % 9 6 6 & . ( 1 & % $ 9 ' ' 4 $ $ 9 ' ' 4 9 ' ' 9 6 6 1 & 3 $ 5 b , 1 $ $ 3 9 ' ' 4 & $ 6 1 & 6 9 ' ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 6 & / 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 & % ' 4 6 9 6 6 & % 9 ' ' 4 9 ' ' 1 & ( 3 5 b 2 8 7 $ 9 ' ' $ $ 9 6 6 9 ' ' 9 ' ' % $ : ( 9 ' ' 4 1 & 2 ' 7 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 6 $ 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 6 ' $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 6 1 & 9 6 6 ' 4 9 6 6 1 & ' 4 6 ' 4 9 6 6 ' 4 ' 0 ' 4 6 9 6 6 1 & ' 4 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 6 ' 4 9 6 6 & % ' 0 ' 4 6 9 6 6 & % 9 ' ' 4 9 ' ' 1 & $ $ 9 ' ' $ $ 9 ' ' & . $ % $ 5 $ 6 9 ' ' 4 1 & $ 9 6 6 ' 4 ' 0 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 6 ' 4 9 6 6 ' 4 1 & 6 9 6 6 1 & ' 4 6 ' 4 9 6 6 ' 4 ' 0 ' 4 6 9 6 6 ' 4 9 ' ' 6 3 ' 6 $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 1 & ' 4 6 ' 4 9 6 6 ' 4 ' 0 ' 4 6 9 6 6 ' 4 & % 9 6 6 1 & ' 4 6 & % 9 6 6 1 & & . ( 1 & $ 9 ' ' 4 $ $ 9 ' ' 4 $ & . 9 ' ' 9 ' ' 9 ' ' 4 6 2 ' 7 9 ' ' ' 4 9 6 6 1 & ' 4 6 ' 4 9 6 6 ' 4 ' 0 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 1 & 6 ' 0 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 6 ' 4 9 6 6 6 $ ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( internet data sheet rev. 1.0, 2007-07 14 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 3 electrical characteristics this chapter lists the el ectrical characteristics. 3.1 absolute maximum ratings caution is needed not to exceed absolute maximum ratings of the dram device listed in table 8 at any time. table 8 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. table 9 dram component operating temperature range symbol parameter rating unit notes min. max. v dd voltage on v dd pin relative to v ss ?1.0 +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 +2.3 v 1)2) v ddl voltage on v ddl pin relative to v ss ?0.5 +2.3 v 1)2) v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v 1) t stg storage temperature ?55 +100 c 1)2) 2) storage temperature is the case surface temperature on the center/top side of the dram. symbol parameter rating unit notes min. max. t oper operating temperature 0 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dram specification will be supported. during operation, the dr am case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c tcase tem perature range, the high temperature self refresh has to be enable d by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50% internet data sheet rev. 1.0, 2007-07 15 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 3.2 dc operating conditions this chapter contains the dc operating conditions tables. table 10 operating conditions table 11 supply voltage levels an d dc operating conditions parameter symbol values unit note min. max. operating temperature (ambient) t opr 0+65 c dram case temperature t case 0+95 c 1)2)3)4) 1) dram component case temperature is the surface temperature in the center on the top side of any of the drams. 2) within the dram component case temperature range all dram specificat ions will be supported 3) above 85 c dram case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c t case temperature range, the high temperature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50%. storage temperature t stg ? 50 +100 c barometric pressure (operating & storage) pbar +69 +105 kpa 5) 5) up to 3000 m. operating humidity (relative) h opr 10 90 % storage humidity (without condensation) h stg 595% parameter symbol values unit notes min. typ. max. device supply voltage v dd 1.7 1.8 1.9 v output supply voltage v ddq 1.7 1.8 1.9 v 1) 1) under all conditions, v ddq must be less than or equal to v dd input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc). v ref is also expected to track noise in v ddq . spd supply voltage v ddspd 1.7 ? 3.6 v dc input logic high v ih(dc) v ref + 0.125 ? v ddq +0.3 v dc input logic low v il (dc ) ? 0.30 ? v ref ? 0.125 v in / output leakage current i l ? 5 ? 5 a 3) 3) input voltage for any connector pin under test of 0 v v in v ddq + 0.3 v; all other pins at 0 v. current is per pin internet data sheet rev. 1.0, 2007-07 16 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 3.3 timing characteristics this chapter describes the timing characteristics. 3.3.1 speed grade definitions all speed grades faster than ddr2-400b comp ly with ddr2-400b timing specifications( t ck = 5ns with t ras = 40ns). speed grade definitions: table 12 for ddr2?800e , table 13 for ddr2?667d, table 14 for ddr2?533c table 12 speed grade definition speed bins for ddr2?800 table 13 speed grade definition speed bins for ddr2?667 speed grade ddr2?800d ddr2?800e unit note qag sort name ?2.5f ?2.5 cas-rcd-rp latencies 5?5?5 6?6?6 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 58 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 2.5 8 3 8 ns 1)2)3)4) @ cl = 6 t ck 2.5 8 2.5 8 ns 1)2)3)4) row active time t ras 45 70000 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 dev ice can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 57.5 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 12.5 ? 15 ? ns 1)2)3)4) row precharge time t rp 12.5 ? 15 ? ns 1)2)3)4) speed grade ddr2?667c ddr2?667d unit notes qag sort name ?3 ?3s cas-rcd-rp latencies 4?4?4 5?5?5 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 5858ns 1)2)3)4) @ cl = 4 t ck 383.758ns 1)2)3)4) @ cl = 5 t ck 3838ns 1)2)3)4) internet data sheet rev. 1.0, 2007-07 17 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module table 14 speed grade definition speed bins for ddr2?533c row active time t ras 45 70000 45 70000 ns 1)2)3)4)5) row cycle time t rc 57 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 12 ? 15 ? ns 1)2)3)4) row precharge time t rp 12 ? 15 ? ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) . 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . 5) t ras.max is calculated from the maximum amount of time a ddr2 dev ice can operate without a refresh command which is equal to 9 x t refi . speed grade ddr2?533c unit note qag sort name ?3.7 cas-rcd-rp latencies 4?4?4 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode.timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 3.75 8 ns 1)2)3)4) row active time t ras 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4) speed grade ddr2?667c ddr2?667d unit notes qag sort name ?3 ?3s cas-rcd-rp latencies 4?4?4 5?5?5 t ck parameter symbol min. max. min. max. ? internet data sheet rev. 1.0, 2007-07 18 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 3.3.2 component ac timing parameters timing parameters: table 15 for ddr2?800e, table 16 for ddr2?667d, table 17 for ddr2?533c table 15 dram component timing parameter by speed grade - ddr2?800 parameter symbol ddr2?800 unit notes 1)2)3)4)5)6) 7)8) min. max. dq output access time from ck / ck t ac ?400 +400 ps 9) cas to cas command delay t ccd 2?nck average clock high pulse width t ch.avg 0.48 0.52 t ck.avg 10)11) average clock period t ck.avg 2500 8000 ps 10)11) cke minimum pulse width ( high and low pulse width) t cke 3?nck 12) average clock low pulse width t cl.avg 0.48 0.52 t ck.avg 10)11) auto-precharge write recovery + precharge time t dal wr + t nrp ?nck 13)14) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck .avg + t ih ?? ns dq and dm input hold time t dh.base 125 ?? ps 19)20)15) dq and dm input pulse width for each input t dipw 0.35 ? t ck.avg dqs output access time from ck / ck t dqsck ?350 +350 ps 9) dqs input high pulse width t dqsh 0.35 ? t ck.avg dqs input low pulse width t dqsl 0.35 ? t ck.avg dqs-dq skew for dqs & associated dq signals t dqsq ? 200 ps 16) dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 t ck.avg 17) dq and dm input setup time t ds.base 50 ?? ps 18)19)20) dqs falling edge hold time from ck t dsh 0.2 ? t ck.avg 17) dqs falling edge to ck setup time t dss 0.2 ? t ck.avg 17) four activate window for 1kb page size products t faw 35 ? ns 35) four activate window for 2kb page size products t faw 45 ? ns 35) ck half pulse width t hp min( t ch.abs , t cl.abs ) __ ps 21) data-out high-impedance time from ck / ck t hz ? t ac.max ps 9)22) address and control input hold time t ih.base 250 ? ps 23)25) control & address input pulse width for each input t ipw 0.6 ? t ck.avg address and control input setup time t is.base 175 ? ps 24)25) dq low impedance time from ck/ck t lz.dq 2x t ac.min t ac.max ps 9)22) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max ps 9)22) mrs command to odt update delay t mod 012ns 35) mode register set command cycle time t mrd 2?nck ocd drive mode output delay t oit 012ns 35) dq/dqs output hold time from dqs t qh t hp ? t qhs ?ps 26) internet data sheet rev. 1.0, 2007-07 19 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module dq hold skew factor t qhs ? 300 ps 27) average periodic refresh interval t refi ?7.8 s 28)29) ?3.9 s 29)30) auto-refresh to active/auto-refresh command period t rfc 127.5 ? ns 31) precharge-all (8 banks) command period t rp t rp +1 t ck ?ns read preamble t rpre 0.9 1.1 t ck.avg 32)33) read postamble t rpst 0.4 0.6 t ck.avg 32)34) active to active command period for 1kb page size products t rrd 7.5 ? ns 35) active to active command period for 2kb page size products t rrd 10 ? ns 35) internal read to precharge command delay t rtp 7.5 ? ns 35) write preamble t wpre 0.35 ? t ck.avg write postamble t wpst 0.4 0.6 t ck.avg write recovery time t wr 15 ? ns 35) internal write to read command delay t wtr 7.5 ? ns 35)36) exit power down to read command t xard 2?nck exit active power-down mode to read command (slow exit, lower power) t xards 8 ? al ? nck exit precharge power-down to any valid command (other than nop or deselect) t xp 2?nck exit self-refresh to a non-read command t xsnr t rfc +10 ? ns 35) exit self-refresh to read command t xsrd 200 ? nck write command to dqs associated clock edges wl rl ? 1 nck 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . 9) when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for ex ample, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 10) input clock jitter spec parameter. these parameters are referred to as 'input cl ock jitter spec parameters' and these param eters apply to ddr2?667 and ddr2?800 only. the jitter specified is a random jitter meeting a gaussian distribution. parameter symbol ddr2?800 unit notes 1)2)3)4)5)6) 7)8) min. max. internet data sheet rev. 1.0, 2007-07 20 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 11) these parameters are specified per their average values, howev er it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of spec values are to be used for calculations ). 12) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 clo cks of registration. thus, after any cke tr ansition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . 13) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 14) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 15) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is refe renced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see figure 3 . 16) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. 17) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 18) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is referenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a ri sing signal, and from the input signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal applied to the devic e under test. dqs, dqs signals must be monotonic between v il(dc)max and v ih(dc)min . see figure 3 . 19) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 20) these parameters are measured from a data signal ((l/u)dm, (l/u)dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 21) t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. 22) t hz and t lz transitions occur in the same access time as valid data trans itions. these parameters are refe renced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 23) input waveform timing is referenced from the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see figure 4 . 24) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see figure 4 . 25) these parameters are measured from a command/address signal (c ke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal cr ossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 26) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 27) t qhs accounts for: 1) the pulse duration distortion of on-ch ip clock circuits, which repr esents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers. 28) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 29) 0 c t case 85 c 30) 85 c < t case 95 c 31) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 32) t rpst end point and t rpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). figure 2 shows a method to calculate these points when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement poi nts are not critical as long as the calculation is consistent. internet data sheet rev. 1.0, 2007-07 21 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module table 16 dram component timing parameter by speed grade - ddr2?667 33) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!). 34) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for ex ample, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 35) for these parameters, the ddr2 sdram device is characterized and verified to support t nparam = ru{ t param / t ck.avg }, which is in clock cycles, assuming all input cl ock jitter specifications are satisfied. for example, the device will support t nrp = ru{ t rp / t ck.avg }, which is in clock cycles, if all input clock jitter specifications are me t. this means: for ddr2?667 5?5?5, of which t rp = 15 ns, the device will support t nrp = ru{ t rp / t ck.avg } = 5, i.e. as long as the input cloc k jitter specifications are met, prechar ge command at tm and active command at tm + 5 is valid even if (tm + 5 - tm) is less than 15 ns due to input clock jitter. 36) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. parameter symbol ddr2?667 unit notes 1)2)3)4)5)6) 7)8) min. max. dq output access time from ck / ck t ac ?450 +450 ps 9) cas to cas command delay t ccd 2?nck average clock high pulse width t ch.avg 0.48 0.52 t ck.avg 10)11) average clock period t ck.avg 3000 8000 ps cke minimum pulse width ( high and low pulse width) t cke 3?nck 12) average clock low pulse width t cl.avg 0.48 0.52 t ck.avg 10)11) auto-precharge write recovery + precharge time t dal wr + t nrp ?nck 13)14) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck .avg + t ih ?? ns dq and dm input hold time t dh.base 175 ?? ps 19)20)15) dq and dm input pulse width for each input t dipw 0.35 ? t ck.avg dqs output access time from ck / ck t dqsck ?400 +400 ps 9) dqs input high pulse width t dqsh 0.35 ? t ck.avg dqs input low pulse width t dqsl 0.35 ? t ck.avg dqs-dq skew for dqs & associated dq signals t dqsq ? 240 ps 16) dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 t ck.avg 17) dq and dm input setup time t ds.base 100 ?? ps 18)19)20) dqs falling edge hold time from ck t dsh 0.2 ? t ck.avg 17) dqs falling edge to ck setup time t dss 0.2 ? t ck.avg 17) four activate window for 1kb page size products t faw 37.5 ? ns 35) four activate window for 2kb page size products t faw 50 ? ns 35) ck half pulse width t hp min( t ch.abs , t cl.abs ) __ ps 21) data-out high-impedance time from ck / ck t hz ? t ac.max ps 9)22) address and control input hold time t ih.base 275 ? ps 25)23) internet data sheet rev. 1.0, 2007-07 22 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module control & address input pulse width for each input t ipw 0.6 ? t ck.avg address and control input setup time t is.base 200 ? ps 24)25) dq low impedance time from ck/ck t lz.dq 2x t ac.min t ac.max ps 9)22) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max ps 9)22) mrs command to odt update delay t mod 012ns 35) mode register set command cycle time t mrd 2?nck ocd drive mode output delay t oit 012ns 35) dq/dqs output hold time from dqs t qh t hp ? t qhs ?ps 26) dq hold skew factor t qhs ? 340 ps 27) average periodic refresh interval t refi ?7.8 s 28)29) ?3.9 s 29)30) auto-refresh to active/auto-refresh command period t rfc 127.5 ? ns 31) precharge-all (8 banks) command period t rp t rp +1 t ck ?ns read preamble t rpre 0.9 1.1 t ck.avg 32)33) read postamble t rpst 0.4 0.6 t ck.avg 32)34) active to active command period for 1kb page size products t rrd 7.5 ? ns 35) active to active command period for 2kb page size products t rrd 10 ? ns 35) internal read to precharge command delay t rtp 7.5 ? ns 35) write preamble t wpre 0.35 ? t ck.avg write postamble t wpst 0.4 0.6 t ck.avg write recovery time t wr 15 ? ns 35) internal write to read command delay t wtr 7.5 ? ns 35)36) exit power down to read command t xard 2?nck exit active power-down mode to read command (slow exit, lower power) t xards 7 ? al ? nck exit precharge power-down to any valid command (other than nop or deselect) t xp 2?nck exit self-refresh to a non-read command t xsnr t rfc +10 ? ns 35) exit self-refresh to read command t xsrd 200 ? nck write command to dqs associated clock edges wl rl?1 nck 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . parameter symbol ddr2?667 unit notes 1)2)3)4)5)6) 7)8) min. max. internet data sheet rev. 1.0, 2007-07 23 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 8) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . 9) when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for ex ample, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 10) input clock jitter spec parameter. these parameters are referred to as 'input cl ock jitter spec parameters' and these param eters apply to ddr2?667 and ddr2?800 only. the jitter specified is a random jitter meeting a gaussian distribution. 11) these parameters are specified per their average values, howev er it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of spec values are to be used for calculations ). 12) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 clo cks of registration. thus, after any cke tr ansition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . 13) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 14) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 15) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is refe renced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see figure 3 . 16) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. 17) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 18) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is referenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a ri sing signal, and from the input signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal applied to the devic e under test. dqs, dqs signals must be monotonic between v il(dc)max and v ih(dc)min . see figure 3 . 19) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 20) these parameters are measured from a data signal ((l/u)dm, (l/u)dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 21) t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. 22) t hz and t lz transitions occur in the same access time as valid data trans itions. these parameters are refe renced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 23) input waveform timing is referenced from the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see figure 4 . 24) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see figure 4 . 25) these parameters are measured from a command/address signal (c ke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal cr ossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 26) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 27) t qhs accounts for: 1) the pulse duration distortion of on-ch ip clock circuits, which repr esents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers. internet data sheet rev. 1.0, 2007-07 24 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module figure 2 method for calculating transitions and endpoint figure 3 differential input waveform timing - t ds and t ds 28) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 29) 0 c t case 85 c 30) 85 c < t case 95 c 31) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 32) t rpst end point and t rpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). figure 2 shows a method to calculate these points when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement poi nts are not critical as long as the calculation is consistent. 33) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!). 34) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for ex ample, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 35) for these parameters, the ddr2 sdram device is characterized and verified to support t nparam = ru{ t param / t ck.avg }, which is in clock cycles, assuming all input cl ock jitter specifications are satisfied. for example, the device will support t nrp = ru{ t rp / t ck.avg }, which is in clock cycles, if all input clock jitter specifications are me t. this means: for ddr2?667 5?5?5, of which t rp = 15 ns, the device will support t nrp = ru{ t rp / t ck.avg } = 5, i.e. as long as the input cloc k jitter specifications are met, prechar ge command at tm and active command at tm + 5 is valid even if (tm + 5 - tm) is less than 15 ns due to input clock jitter. 36) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. w + = w 5 3 6 7 h q g s r l q w 7 7 9 2 + [ p 9 9 2 + [ p 9 9 2 / [ p 9 9 2 / [ p 9 w / = w 5 3 5 ( e h j l q s r l q w 7 7 9 7 7 [ p 9 9 7 7 [ p 9 9 7 7 [ p 9 9 7 7 [ p 9 w / = w 5 3 5 ( e h j l q s r l q w 7 7 w + = w 5 3 6 7 h q g s r l q w 7 7 w ' 6 9 ' ' 4 9 , + d f p l q 9 , + g f p l q 6 2 % & d c 9 , / g f p d [ 9 , / d f p d [ 9 6 6 ' 4 6 ' 4 6 w ' + w ' 6 w ' + internet data sheet rev. 1.0, 2007-07 25 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module figure 4 differential input waveform timing - t ls and t lh w , 6 9 ' ' 4 9 , + d f p l q 9 , + g f p l q 9 5 ( ) g f 9 , / g f p d [ 9 , / d f p d [ 9 6 6 & . & . w , + w , 6 w , + internet data sheet rev. 1.0, 2007-07 26 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module table 17 dram component timing parameter by speed grade - ddr2?533 parameter symbol ddr2?533 unit notes 1)2)3)4)5) 6)7) min. max. dq output access time from ck / ck t ac ?500 +500 ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 8)18) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns 9) dq and dm input hold time (differential data strobe) t dh (base) 225 ?? ps 10) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps 11) dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ?450 + 450 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ps 11) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setup time (differential data strobe) t ds (base) 100 ? ps 11) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps 11) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck four activate window period t faw 37.5 ? ns four activate window period t faw 50 ? ns 13) clock half period t hp min. ( t cl, t ch ) 12) data-out high-impedance time from ck / ck t hz ? t ac.max ps 13) address and control input hold time t ih (base) 375 ? ps 11) address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 250 ? ps 11) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps 14) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 14) mrs command to odt update delay t mod 012ns mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns internet data sheet rev. 1.0, 2007-07 27 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module data output hold time from dqs t qh t hp ? t qhs ? data hold skew factor t qhs ? 400 ps average periodic refresh interval t refi ?7.8 s 14)15) average periodic refresh interval t refi ?3.9 s 16)18) auto-refresh to active/auto-refresh command period t rfc 127.5 ? ns 17) precharge-all (8 banks) command period t rp t rp +1 t ck ?ns read preamble t rpre 0.9 1.1 t ck 14) read postamble t rpst 0.40 0.60 t ck 14) active bank a to active bank b command period t rrd 7.5 ? ns 14)18) active bank a to active bank b command period t rrd 10 ? ns 16)22) internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 ? t ck write postamble t wpst 0.40 0.60 t ck 19) write recovery time for write without auto- precharge t wr 15 ? ns internal write to read command delay t wtr 7.5 ? ns 20) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 21) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 21) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck write recovery time for write with auto- precharge wr t wr / t ck t ck 22) 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 9) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) for timing definition, refer to the component data sheet. 11) consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of t he output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. parameter symbol ddr2?533 unit notes 1)2)3)4)5) 6)7) min. max. internet data sheet rev. 1.0, 2007-07 28 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 12) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the act ual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 13) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 14) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 15) 0 c t case 85 c 16) 85 c < t case 95 c 17) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 18) the t rrd timing parameter depends on the page size of the dram organization. see table 2 ?ordering information for rohs compliant products? on page 4 . 19) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 21) user can choose two different active pow er-down modes for additional power saving vi a mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. 22) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. internet data sheet rev. 1.0, 2007-07 29 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 3.3.3 odt ac electrical characteristics this chapter describes the odt ac electrical characteristics. table 18 odt ac characteristics and operating conditions for all bins ddr2-667 & ddr2-800 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 n ck 1) 1) new units, ?t ck.avg ? and ? n ck ?, are introduced in ddr2-667 and ddr2-800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ? n ck ? represents one clock cycle of the input clock, count ing the actual clock edges. note that in ddr2-400 and ddr2-533, ? t ck ? is used for both concepts. example: t xp = 2 [ n ck ] means; if power down exit is registered at t m , an active command may be registered at t m + 2, even if ( t m + 2 - t m ) is 2 x t ck.avg + t err.2per(min) . t aon odt turn-on t ac.min t ac.max + 0.7 ns ns 1)2) 2) odt turn on time min is when the device leaves high impedance and odt re sistance begins to turn on. odt turn on time max is w hen the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-667/800, t aond is 2 clock cycles after the clock edge that registered a firs t odt high counting the actual input clock edges. t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns 1) t aofd odt turn-off delay 2.5 2.5 n ck 1) t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 1)3) 3) odt turn off time min is when the device starts to turn off od t resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-667/800, iif t ck(avg) = 3 ns is assumed, t aofd is 1.5 ns (= 0.5 x 3 ns) after the second trai ling clock edge counting from the clock edge t hat registered a first odt low and by coun ting the actual input clock edges. t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns 1) t anpd odt to power down mode entry latency 3 ? n ck 1) t axpd odt power down exit latency 8 ? n ck 1) internet data sheet rev. 1.0, 2007-07 30 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module table 19 odt ac characteristics and operating conditions for ddr2-533 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min. is when the devic e leaves high impedance and odt re sistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-400/533, t aond is 10 ns (= 2 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-400/533, t aofd is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck internet data sheet rev. 1.0, 2007-07 31 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 3.4 specifications and conditions list of tables defining i dd specifications and conditions. ? table 20 ?idd measurement conditions? on page 31 ? table 21 ?definitions for idd? on page 32 ? table 22 ?idd specification for hys72t1g242ep?[2.5/25f/3/3s/3.7]?c? on page 33 table 20 i dd measurement conditions parameter symbol note 1)2)3)4)5) operating current 0 one bank active - precharge; t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , t rcd = t rcd.min , al = 0, cl = cl min ; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are switching, databus inputs are switching. i dd2n precharge power-down current other control and address inputs are st able, data bus inputs are floating. i dd2p precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are stable, data bus inputs are floating. i dd2q active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max , t rp = t rp.min ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n active power-down current all banks open; t ck = t ck.min , cke is low; other control and addres s inputs are stable, data bus inputs are floating. mrs a12 bit is se t to low (fast power-down exit); i dd3p(0) active power-down current all banks open; t ck = t ck.min , cke is low; other control and addre ss inputs are stable, data bus inputs are floating. mrs a12 bit is set to high (slow power-down exit); i dd3p(1) operating current - burst read all banks open; continuous burst re ads; bl = 4; al = 0, cl = cl min ; t ck = t ckmin ; t ras = t rasmax ; t rp = t rpmin ; cke is high, cs is high between valid co mmands; address inputs are switching; data bus inputs are switching; i out = 0ma. i dd4r 6) operating current - burst write all banks open; continuous burst wr ites; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max. , t rp = t rp.max ; cke is high, cs is high between valid commands. address inputs are switching; data bus in puts are switching; i dd4w burst refresh current t ck = t ck.min ., refresh command every t rfc = t rfc.min interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b internet data sheet rev. 1.0, 2007-07 32 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module table 21 definitions for i dd distributed refresh current t ck = t ck.min. , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5d self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and addr ess inputs are floating, data bus inputs are floating. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 6) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) i dd specifications are tested after t he device is properly initialized and i dd parameter are specified with odt disabled. 3) definitions for i dd see table 21 4) for two rank modules: for all active current meas urements the other rank is in precharge power-down mode i dd2p 5) for details and notes see the relevant qimonda component data sheet 6) i dd1 , i dd4r and i dd7 current measurements are defined with the outputs disabled ( i out = 0 ma). to achieve this on module level the output buffers can be disabled using an emrs(1) (extended m ode register command) by setting a12 bit to high. parameter description low v in v il(ac).max , high is defined as v in v ih(ac).min stable inputs are stable at a high or low level floating inputs are v ref = v ddq /2 switching inputs are changing between hi gh and low every other clock (once per 2 cycles) for address and control signals, and inputs changing between high and low every other data transfer (once per cycle) for dq signals not including mask or strobes parameter symbol note 1)2)3)4)5) internet data sheet rev. 1.0, 2007-07 33 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module table 22 i dd specification for hys72t1g242ep?[2.5/25f/3/3s/3.7]?c product type hys72t1g242ep?2.5?c hys72t1g242ep?25f?c hys72t1g242ep?3?c hys72t1g242ep?3s?c hys72t1g242ep?3.7?c units note 1) 1) module i dd is calculated on the basis of component i dd and includes currents of registers and pll. odt disabled. i dd1, i dd4r, and i dd7, are defined with the outputs disabled. organization 8 gb 8 gb 8 gb 8 gb 8 gb 72 72 72 72 72 4 ranks 4 ranks 4 ranks 4 ranks 4 ranks ?2.5 ?2.5f ?3 ?3s ?3.7 i dd0 4030 4040 3620 3620 3210 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 4100 4120 3700 3700 3260 ma 2) i dd2p 2550 2550 2260 2260 1950 ma 3) 3) both ranks are in the same i dd current mode i dd2n 6650 6650 6000 6000 5190 ma 3) i dd2q 6290 6290 5640 5640 5120 ma 3) i dd3p_0 (fast) 4350 4350 3910 3910 3390 ma 3) i dd3p_1 (slow) 2910 2910 2620 2620 2310 ma 3)4) 4) fast: mrs(12)=0 i dd3n 7010 7010 6220 6220 5410 ma 3)5) 5) slow: mrs(12)=1 i dd4r 5110 5110 4520 4520 3930 ma 2) i dd4w 5200 5200 4610 4610 4020 ma 2) i dd5b 5900 5900 5460 5460 5100 ma 2) i dd5d 2690 2690 2400 2400 2090 ma 3)6) 6) i dd5d and i dd6 values are for 0 c t case 85 c i dd6 720 720 720 720 720 ma 3)6) i dd7 6190 6190 5590 5550 5280 ma 2) internet data sheet rev. 1.0, 2007-07 34 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 4 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 23 ?hys72t1g242ep-[25f/2.5/3/3s/3.7]-c? on page 34 table 23 hys72t1g242ep-[25f/2.5/3/3s/3.7]-c product type hys72t1g242ep?2.5?c hys72t1g242ep?25f?c hys72t1g242ep?3?c hys72t1g242ep?3s?c hys72t1g242ep?3.7?c organization 8 gbyte 8 gbyte 8 gbyte 8 gbyte 8 gbyte 72 72 72 72 72 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) label code pc2? 6400p? 666 pc2? 6400p? 555 pc2? 5300p? 444 pc2? 5300p? 555 pc2? 4200p? 444 jedec spd revision rev. 1.2 rev . 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 08 2 memory type (ddr2) 08 08 08 08 08 3 number of row addresses 0e 0e 0e 0e 0e 4 number of column addresses 0b 0b 0b 0b 0b 5 dimm rank and stacking information 73 73 73 73 73 6data width 4848484848 7 not used 00 00 00 00 00 8interface voltage level 0505050505 9 t ck @ cl max (byte 18) [ns] 25 25 30 30 3d 10 t ac sdram @ cl max (byte 18) [ns] 40 40 45 45 50 11 error correction support (non-ecc, ecc) 06 06 06 06 06 12 refresh rate and type 82 82 82 82 82 internet data sheet rev. 1.0, 2007-07 35 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 13primary sdram width 0404040404 14error checking sdram width 0404040404 15 not used 00 00 00 00 00 16 burst length supported 0c 0c 0c 0c 0c 17 number of banks on sdram device 08 08 08 08 08 18 supported cas latencies 70 70 38 38 38 19 dimm mechanical characteristics 01 01 01 01 01 20 dimm type information 01 01 01 01 01 21 dimm attributes 07 07 07 07 07 22 component attributes 07 07 07 07 07 23 t ck @ cl max -1 (byte 18) [ns] 30 25 30 3d 3d 24 t ac sdram @ cl max -1 [ns] 45 40 45 50 50 25 t ck @ cl max -2 (byte 18) [ns] 3d 3d 50 50 50 26 t ac sdram @ cl max -2 [ns] 50 50 60 60 60 27 t rp.min [ns] 3c 32 30 3c 3c 28 t rrd.min [ns] 1e 1e 1e 1e 1e 29 t rcd.min [ns] 3c 32 30 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 2d 31 module density per rank 02 02 02 02 02 32 t as.min and t cs.min [ns] 17 17 20 20 25 33 t ah.min and t ch.min [ns] 25 25 27 27 37 34 t ds.min [ns] 05 05 10 10 10 35 t dh.min [ns] 12 12 17 17 22 36 t wr.min [ns] 3c 3c 3c 3c 3c product type hys72t1g242ep?2.5?c hys72t1g242ep?25f?c hys72t1g242ep?3?c hys72t1g242ep?3s?c hys72t1g242ep?3.7?c organization 8 gbyte 8 gbyte 8 gbyte 8 gbyte 8 gbyte 72 72 72 72 72 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) label code pc2? 6400p? 666 pc2? 6400p? 555 pc2? 5300p? 444 pc2? 5300p? 555 pc2? 4200p? 444 jedec spd revision rev. 1.2 rev . 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex internet data sheet rev. 1.0, 2007-07 36 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 37 t wtr.min [ns] 1e 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 00 40 t rc and t rfc extension 0636060606 41 t rc.min [ns] 3c 39 39 3c 3c 42 t rfc.min [ns] 7f 7f 7f 7f 7f 43 t ck.max [ns] 80 80 80 80 80 44 t dqsq.max [ns] 14 14 18 18 1e 45 t qhs.max [ns] 1e 1e 22 22 28 46 pll relock time 0f 0f 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 5151515151 48psi(t-a) dram 6060606060 49 ? t 0 (dt0) 4f4f47473f 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 39 39 34 34 31 51 ? t 2p (dt2p) 3d 3d 3d 3d 3d 52 ? t 3n (dt3n) 2c 2c 28 28 23 53 ? t 3p.fast (dt3p fast) 353531312c 54 ? t 3p.slow (dt3p slow) 2424242424 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 46 46 3e 3e 36 56 ? t 5b (dt5b) 24 24 22 22 22 57 ? t 7 (dt7) 2727242324 58psi(ca) pll c4c4c4c4c4 59psi(ca) reg 8c8c8c8c8c 60 ? t pll (dtpll) 70 70 68 68 61 product type hys72t1g242ep?2.5?c hys72t1g242ep?25f?c hys72t1g242ep?3?c hys72t1g242ep?3s?c hys72t1g242ep?3.7?c organization 8 gbyte 8 gbyte 8 gbyte 8 gbyte 8 gbyte 72 72 72 72 72 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) label code pc2? 6400p? 666 pc2? 6400p? 555 pc2? 5300p? 444 pc2? 5300p? 555 pc2? 4200p? 444 jedec spd revision rev. 1.2 rev . 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex internet data sheet rev. 1.0, 2007-07 37 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 61 ? t reg (dtreg) / toggle rate b0 b0 94 94 78 62 spd revision 12 12 12 12 12 63 checksum of bytes 0-62 14 1d d1 03 08 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx 73product type, char 1 3737373737 74product type, char 2 3232323232 75product type, char 3 5454545454 76product type, char 4 3131313131 77product type, char 5 4747474747 78product type, char 6 3232323232 79product type, char 7 3434343434 80product type, char 8 3232323232 81product type, char 9 4545454545 82 product type, char 10 50 50 50 50 50 83 product type, char 11 32 32 33 33 33 84 product type, char 12 2e 35 43 53 2e product type hys72t1g242ep?2.5?c hys72t1g242ep?25f?c hys72t1g242ep?3?c hys72t1g242ep?3s?c hys72t1g242ep?3.7?c organization 8 gbyte 8 gbyte 8 gbyte 8 gbyte 8 gbyte 72 72 72 72 72 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) label code pc2? 6400p? 666 pc2? 6400p? 555 pc2? 5300p? 444 pc2? 5300p? 555 pc2? 4200p? 444 jedec spd revision rev. 1.2 rev . 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex internet data sheet rev. 1.0, 2007-07 38 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 85 product type, char 13 35 46 20 43 37 86 product type, char 14 43 43 20 20 43 87 product type, char 15 20 20 20 20 20 88 product type, char 16 20 20 20 20 20 89 product type, char 17 20 20 20 20 20 90 product type, char 18 20 20 20 20 20 91 module revision code 0x 0x 0x 0x 0x 92 test program revision code xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 128 - 255 blank for customer use ffffffffff product type hys72t1g242ep?2.5?c hys72t1g242ep?25f?c hys72t1g242ep?3?c hys72t1g242ep?3s?c hys72t1g242ep?3.7?c organization 8 gbyte 8 gbyte 8 gbyte 8 gbyte 8 gbyte 72 72 72 72 72 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) 4 ranks ( 4) label code pc2? 6400p? 666 pc2? 6400p? 555 pc2? 5300p? 444 pc2? 5300p? 555 pc2? 4200p? 444 jedec spd revision rev. 1.2 rev . 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hex internet data sheet rev. 1.0, 2007-07 39 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 5 package outlines this chapter contains the package outlines of the products. figure 5 package outline raw card z l-dim-240-49 & 0 / ? , ? $ ) - ? ? ? ? " - ! 8 # ? ? ! ? - ) . $ e t a i l o f c o n t a c t s # ? ! " ? # " ! ? x $ r a w i n g a c c o r d i n g t o ) 3 / ' e n e r a l t o l e r a n c e s ? $ i m e n s i o n s i n m m internet data sheet rev. 1.0, 2007-07 40 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 6 product type nomenclature qimondas nomenclature uses simple codi ng combined with some propriatory coding. table 24 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 25 and for components in table 26 . table 24 nomenclature fields and examples table 25 ddr2 dimm nomenclature example for field number 1234567891011 micro-dimm hys 64 t 64/128 0 2 0 k m ?5 ?a ddr2 dram hyb 18 t 512/1g 16 0 a c ?5 field description values coding 1 qimonda module prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3 dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 512 4 gbyte 5 raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type d so- d imm m m icro-dimm r r egistered u u nbuffered f f ully buffered internet data sheet rev. 1.0, 2007-07 41 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module table 26 ddr2 dram nomenclature 10 speed grade ?2.5f pc2?6400 5?5?5 ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the o verall module memory density in mbytes as listed in column ?coding?. field description values coding 1 qimonda component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free stat us c fbga, lead-containing f fbga, lead-free 10 speed grade ?25f ddr2-800 5-5-5 ?2.5 ddr2-800 6-6-6 ?3 ddr2-667 4-4-4 ?3s ddr2-667 5-5-5 ?3.7 ddr2-533 4-4-4 ?5 ddr2-400 3-3-3 field description values coding internet data sheet rev. 1.0, 2007-07 42 07242007-lr08-ozc0 hys72t1g242ep?[25f/2.5/3/3s/3.7]?c registerd ddr2 sdram module 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configuration and block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.2 component ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6 product type nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table of contents edition 2007-07 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a gua rantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet |
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